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P912XDP512F0MFVR 数据表(PDF) 352 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 352 Page - Freescale Semiconductor, Inc |
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352 / 1350 page  Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.17 352 Freescale Semiconductor Figure 7-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 1 16 BIT MAIN TIMER P1 Comparator TC0H Hold Reg. P0 P3 P2 P4 P5 P6 P7 EDG0 EDG1 EDG2 EDG3 MUX Modulus Prescaler Bus Clock 16-Bit Load Register 16-Bit Modulus 0 RESET EDG0 EDG1 EDG2 EDG4 EDG5 EDG3 EDG6 EDG7 ÷ 1, 2,3, ..., 256 16-Bit Free-Running Main Timer Timer Prescaler TC0 Capture/Compare Reg. Comparator TC1 Capture/Compare Reg. Comparator TC2 Capture/Compare Reg. Comparator TC3 Capture/Compare Reg. Comparator TC4 Capture/Compare Reg. Comparator TC5 Capture/Compare Reg. Comparator TC6 Capture/Compare Reg. Comparator TC7 Capture/Compare Reg. Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Pin Logic Delay TC1H Hold Reg. TC2H Hold Reg. TC3H Hold Reg. MUX MUX MUX PA0H Hold Reg. PAC0 0 RESET PA1H Hold Reg. PAC1 0 RESET PA2H Hold Reg. PAC2 0 RESET PA3H Hold Reg. PAC3 Write 0x0000 to Modulus Counter ICLAT, LATQ, BUFEN (Force Latch) LATQ (MDC Latch Enable) Down Counter SH04 SH15 SH26 SH37 Bus Clock ÷ 1, 2,3, ..., 256 Counter Delay Counter Delay Counter Delay Counter 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 8, 12, 16, ..., 1024 |
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