P912XDP512F0MFVR datasheet(365/1350 Pages) FREESCALE

365 / 1350 page

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

365

8.2.3

PWM5 — PWM Channel 5

This pin serves as waveform output of PWM channel 5.

8.2.4

PWM4 — PWM Channel 4

This pin serves as waveform output of PWM channel 4.

8.2.5

PWM3 — PWM Channel 3

This pin serves as waveform output of PWM channel 3.

8.2.6

PWM3 — PWM Channel 2

This pin serves as waveform output of PWM channel 2.

8.2.7

PWM3 — PWM Channel 1

This pin serves as waveform output of PWM channel 1.

8.2.8

PWM3 — PWM Channel 0

This pin serves as waveform output of PWM channel 0.

8.3

Memory Map and Register Deﬁnition

This section describes in detail all the registers and register bits in the PWM module.

The special-purpose registers and register bit functions that are not normally available to device end users,

such as factory test control registers and reserved registers, are clearly identiﬁed by means of shading the

appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting

access to the registers and functions are also explained in the individual register descriptions.

8.3.1

Module Memory Map

This section describes the content of the registers in the PWM module. The base address of the PWM

module is determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and

begins at the ﬁrst address of the module address offset. The ﬁgure below shows the registers associated

with the PWM and their relative offset from the base address. The register detail description follows the

order they appear in the register map.

Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented

functions are indicated by shading the bit. .

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