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P912XDP512F0MFVR 数据表(PDF) 368 Page - Freescale Semiconductor, Inc

部件名 P912XDP512F0MFVR
功能描述  Covers, S12XD, S12XB & S12XA Families
PDF  1350 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 368 Page - Freescale Semiconductor, Inc

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
368
Freescale Semiconductor
8.3.2.1
PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
PWMPER7
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY1
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY2
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY3
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY4
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY5
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY6
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY7
R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMSDN
R
PWMIF
PWMIE
0
PWMLVL
0
PWM7IN
PWM7INL
PWM7ENA
W
PWMRSTRT
1 Intended for factory test purposes only.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 8-2. PWM Register Summary (Sheet 3 of 3)



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