P912XDP512F0MFVR datasheet(371/1350 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

371

NOTE

changed while a PWM signal is being generated, a truncated or stretched

pulse can occur during the transition.

8.3.2.4

PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently.

Read: Anytime

Write: Anytime

Table 8-3. PWMCLK Field Descriptions

Field

Description

PCLK7

Pulse Width Channel 7 Clock Select

0 Clock B is the clock source for PWM channel 7.

1 Clock SB is the clock source for PWM channel 7.

PCLK6

Pulse Width Channel 6 Clock Select

0 Clock B is the clock source for PWM channel 6.

1 Clock SB is the clock source for PWM channel 6.

PCLK5

Pulse Width Channel 5 Clock Select

0 Clock A is the clock source for PWM channel 5.

1 Clock SA is the clock source for PWM channel 5.

PCLK4

Pulse Width Channel 4 Clock Select

0 Clock A is the clock source for PWM channel 4.

1 Clock SA is the clock source for PWM channel 4.

PCLK3

Pulse Width Channel 3 Clock Select

0 Clock B is the clock source for PWM channel 3.

1 Clock SB is the clock source for PWM channel 3.

PCLK2

Pulse Width Channel 2 Clock Select

0 Clock B is the clock source for PWM channel 2.

1 Clock SB is the clock source for PWM channel 2.

PCLK1

Pulse Width Channel 1 Clock Select

0 Clock A is the clock source for PWM channel 1.

1 Clock SA is the clock source for PWM channel 1.

PCLK0

Pulse Width Channel 0 Clock Select

0 Clock A is the clock source for PWM channel 0.

1 Clock SA is the clock source for PWM channel 0.

76543210

PCKB2

PCKB1

PCKB0

PCKA2

PCKA1

PCKA0

Reset

00000000

= Unimplemented or Reserved

Figure 8-6. PWM Prescale Clock Select Register (PWMPRCLK)

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