P912XDP512F0MFVR datasheet(381/1350 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

381

8.4.1.1

Prescale

The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze

mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze

mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation

in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are

disabled (PWME7-0 = 0). This is useful for reducing power by disabling the prescale counter.

Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock

A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value

selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The

value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK

8.4.1.2

Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and

then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user

programmable value and then divides this by 2. The rates available for clock SA are software selectable to

be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock

SB.

P912XDP512F0MFVR 数据表(PDF) 381 Page - Freescale Semiconductor, Inc