P912XDP512F0MFVR datasheet(384/1350 Pages) FREESCALE

384 / 1350 page

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.17

384

Freescale Semiconductor

8.4.2

PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period

the period register and the value in the counter. The duty is controlled by a match between the duty register

and the counter value and causes the state of the output to change during the period. The starting polarity

of the output is also selectable on a per channel basis. Shown below in Figure 8-19 is the block diagram

for the PWM timer.

Figure 8-19. PWM Timer Channel Block Diagram

8.4.2.1

PWM Enable

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx

bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual

PWM waveform is not available on the associated PWM output until its clock source begins its next cycle

due to the synchronization of PWMEx and the clock source. An exception to this is when channels are

concatenated. Refer to Section 8.4.2.7, “PWM 16-Bit Functions” for more detail.

NOTE

The ﬁrst PWM cycle after enabling the channel can be irregular.

Clock Source

PPOLx

From Port PWMP

Data Register

PWMEx

To Pin

Driver

Gate

8-bit Compare =

PWMDTYx

8-bit Compare =

PWMPERx

CAEx

8-Bit Counter

PWMCNTx

(Clock Edge

Sync)

Up/Down

Reset

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