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P912XDP512F0MFVR 数据表(PDF) 389 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 389 Page - Freescale Semiconductor, Inc |
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389 / 1350 page ![]() Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 389 To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. • PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx) • PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% |
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