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P912XDP512F0MFVR 数据表(PDF) 443 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 443 Page - Freescale Semiconductor, Inc |
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443 / 1350 page  Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 443 10.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Table 10-21. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7:0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3) 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 00000 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 00000 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 00000 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 00000 Figure 10-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3 |
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