P912XDP512F0MFVR datasheet(503/1350 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

503

indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control

11.4.6.3

Data Sampling

The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust

for baud rate mismatch, the RT clock (see Figure 11-21) is re-synchronized:

•

After every start bit

•

After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit

samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic

1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Figure 11-21. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

Figure 11-16 summarizes the results of the start bit veriﬁcation samples.

If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins.

Table 11-16. Start Bit Veriﬁcation

RT3, RT5, and RT7 Samples

Start Bit Veriﬁcation

Noise Flag

000

Yes

001

Yes

010

Yes

011

100

Yes

101

110

111

Reset RT Clock

Samples

RT Clock

RT CLock Count

Start Bit

RXD

Start Bit

Qualiﬁcation

Start Bit

Data

Sampling

LSB

Veriﬁcation

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