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P912XDP512F0MFVR 数据表(PDF) 505 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 505 Page - Freescale Semiconductor, Inc |
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505 / 1350 page ![]() Chapter 11 Serial Communication Interface (S12SCIV5) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 505 In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found. Figure 11-22. Start Bit Search Example 1 In Figure 11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Figure 11-23. Start Bit Search Example 2 Reset RT Clock Samples RT Clock RT Clock Count Start Bit RXD 11 0 1 11 1 0 0 0 00 LSB 0 0 Reset RT Clock Samples RT Clock RT Clock Count Actual Start Bit RXD 11 1 1 11 0 0 0 0 LSB 0 0 Perceived Start Bit |
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