P912XDP512F0MFVR datasheet(509/1350 Pages) FREESCALE

509 / 1350 page

Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

509

11.4.6.5.2

Fast Data Tolerance

Figure 11-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10

instead of RT16 but is still sampled at RT8, RT9, and RT10.

Figure 11-29. Fast Data

For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 11-29, the receiver counts 154 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit

character with no errors is:

((160 – 154) / 160) x 100 = 3.75%

For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles

to ﬁnish data sampling of the stop bit.

With the misaligned character shown in Figure 11-29, the receiver counts 170 RTr cycles at the point when

the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit

character with no errors is:

((176 – 170) /176) x 100 = 3.40%

11.4.6.6

Receiver Wakeup

To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems,

the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2

(SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will

still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag.

The transmitting device can address messages to selected receivers by including addressing information in

the initial frame or frames of each message.

The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby

state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark

wakeup.

Idle or Next Frame

Stop

Data

Samples

Receiver

RT Clock

P912XDP512F0MFVR 数据表(PDF) 509 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 509 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载