P912XDP512F0MFVR datasheet(595/1350 Pages) FREESCALE

595 / 1350 page

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

595

Chapter 16

Interrupt (S12XINTV1)

16.1

Introduction

The XINT module decodes the priority of all system exception requests and provides the applicable vector

for processing the exception to either the CPU or the XGATE module. The XINT module supports:

•

I bit and X bit maskable interrupt requests

•

A non-maskable unimplemented opcode trap

•

A non-maskable software interrupt (SWI) or background debug mode request

•

A spurious interrupt vector request

•

Three system reset vector requests

Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a

ﬂexible priority scheme. For interrupt requests that are conﬁgured to be handled by the CPU, the priority

scheme can be used to implement nested interrupt capability where interrupts from a lower level are

automatically blocked if a higher level interrupt is being processed. Interrupt requests conﬁgured to be

handled by the XGATE module cannot be nested because the XGATE module cannot be interrupted while

processing.

NOTE

The HPRIO register and functionality of the XINT module is no longer

supported, since it is superseded by the 7-level interrupt request priority

scheme.

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