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P912XDP512F0MFVR 数据表(PDF) 695 Page - Freescale Semiconductor, Inc

部件名 P912XDP512F0MFVR
功能描述  Covers, S12XD, S12XB & S12XA Families
PDF  1350 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 695 Page - Freescale Semiconductor, Inc

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Chapter 19 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
695
XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE
module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG
module armed, the DBG remains armed.
The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if
the MCU is secure.
19.1.4
Block Diagram
Figure 19-1 shows a block diagram of the debug module.
Figure 19-1. Debug Block Diagram
19.2
External Signal Description
The DBG sub-module features two external tag input signals (see Table 19-2). See Device User Guide
(DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging
in emulation modes only
Table 19-1. Mode Dependent Restriction Summary
BDM
Enable
BDM
Active
MCU
Secure
Comparator Matches
Enabled
Breakpoints
Possible
Tagging
Possible
Tracing
Possible
x
x
1
Yes
Yes
Yes
No
0
0
0
Yes
Only SWI
Yes
Yes
0
1
0
Active BDM not possible when not enabled
1
0
0
Yes
Yes
Yes
Yes
1
1
0
XGATE only
XGATE only
XGATE only
XGATE only
CPU BUS
TRIGGER
EXTERNAL TAGHI / TAGLO
MATCH0
XGATE BUS
COMPARATOR B
COMPARATOR C
COMPARATOR D
COMPARATOR A
MATCH1
MATCH2
MATCH3
READ TRACE DATA (DBG READ DATA BUS)
SECURE
BREAKPOINT REQUESTS
XGATE S/W BREAKPOINT REQUEST
TAGS
TAGHITS
STATE
CPU & XGATE
TAG &
TRIGGER
CONTROL
LOGIC
STATE
SEQUENCER
TRACE
BUFFER
TRACE
CONTROL
TRIGGER



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