P912XDP512F0MFVR datasheet(697/1350 Pages) FREESCALE

697 / 1350 page

Chapter 19 Debug (S12XDBGV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

697

19.3

Memory Map and Register Deﬁnition

A summary of the registers associated with the DBG sub-block is shown in Figure 19-2. Detailed

descriptions of the registers and bits are given in the subsections that follow.

19.3.1

This section consists of the DBG control and trace buffer register descriptions in address order. Each

comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F

in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module

registers that can be written are ARM, TRIG and COMRV[1:0]

Address

Name

Bit 7

654321

Bit 0

0x0020

DBGC1

ARM

XGSBPE

BDM

DBGBRK

COMRV

TRIG

0x0021

DBGSR

TBF

EXTF

SSF2

SSF1

SSF0

0x0022

DBGTCR

TSOURCE

TRANGE

TRCMOD

TALIGN

0x0023

DBGC2

0000

CDCM

ABCM

0x0024

DBGTBH

Bit 15

Bit 8

0x0025

DBGTBL

Bit 7

654321

Bit 0

0x0026

DBGCNT

CNT

0x0027

DBGSCRX

0000

SC3

SC2

SC1

SC0

0x0028

DBGXCTL1

(COMPA/C)

NDB

TAG

BRK

RWE

SRC

COMPE

0x0028

DBGXCTL2

(COMPB/D)

SZE

TAG

BRK

RWE

SRC

COMPE

1. This represents the contents if the comparator A or C control register is blended into this address

2. This represents the contents if the comparator B or D control register is blended into this address

= Unimplemented or Reserved

Figure 19-2. DBG Register Summary

P912XDP512F0MFVR 数据表(PDF) 697 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 697 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载