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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.17

752

Freescale Semiconductor

20.3.2.2

Debug Status Register (DBGSR)

Read: Anytime

Write: Never

Address: 0x0021

76543210

TBF

EXTF

SSF2

SSF1

SSF0

Reset

POR

—

= Unimplemented or Reserved

Figure 20-4. Debug Status Register (DBGSR)

Table 20-6. DBGSR Field Descriptions

Field

Description

TBF

Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was

last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].

The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset

initialization. Other system generated resets have no affect on this bit

EXTF

External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was

met since arming. This bit is cleared when ARM in DBGC1 is written to a one.

0 External tag hit has not occurred

1 External tag hit has occurred

2–0

SSF[2:0]

State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During

a debug session on each transition to a new state these bits are updated. If the debug session is ended by

software clearing the ARM bit, then these bits retain their value to reﬂect the last state of the state sequencer

before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0

and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state

sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 20-7

Table 20-7. SSF[2:0] — State Sequence Flag Bit Encoding

SSF[2:0]

Current State

000

State0 (disarmed)

001

State1

010

State2

011

State3

100

Final State

101,110,111

Reserved

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