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P912XDP512F0MFVR 数据表(PDF) 754 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 754 Page - Freescale Semiconductor, Inc |
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754 / 1350 page ![]() Chapter 20 S12X Debug (S12XDBGV3) Module MC9S12XDP512 Data Sheet, Rev. 2.17 754 Freescale Semiconductor Table 20-10. TRANGE Trace Range Encoding TRANGE Tracing Range 00 Trace from all addresses (No filter) 01 Trace only in address range from $00000 to Comparator D 10 Trace only in address range from Comparator C to $7FFFFF 11 Trace only in range from Comparator C to Comparator D Table 20-11. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 20-12. TALIGN Trace Alignment Encoding TALIGN Description 00 Trigger at end of stored data 01 Trigger before storing data 10 Trace buffer entries before and after trigger 11 Reserved |
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