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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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P912XDP512F0MFVR 数据表(PDF) 758 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MFVR 数据表(HTML) 758 Page - Freescale Semiconductor, Inc |
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758 / 1350 page  Chapter 20 S12X Debug (S12XDBGV3) Module MC9S12XDP512 Data Sheet, Rev. 2.17 758 Freescale Semiconductor 20.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 20-19. State Control Register Access Encoding COMRV Visible State Control Register 00 DBGSCR1 01 DBGSCR2 10 DBGSCR3 11 DBGMFR |
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