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P912XDP512F0MFVR 数据表(PDF) 800 Page - Freescale Semiconductor, Inc

部件名 P912XDP512F0MFVR
功能描述  Covers, S12XD, S12XB & S12XA Families
PDF  1350 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 800 Page - Freescale Semiconductor, Inc

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Chapter 21 External Bus Interface (S12XEBIV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
800
Freescale Semiconductor
21.4.5.2
Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, R/W, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 21-18.
Table 21-17. Access in Normal Expanded Mode
Access
RE WE UDS LDS
DATA[15:8]
DATA[7:0]
I/O data(addr) I/O data(addr)
Word write of data on DATA[15:0] at an even and even+1 address
1
0
0
0
Out data(even) Out
data(odd)
Byte write of data on DATA[7:0] at an odd address
1
0
1
0
In
x
Out
data(odd)
Byte write of data on DATA[15:8] at an even address
1
0
0
1
Out data(even)
In
x
Word read of data on DATA[15:0] at an even and even+1 address
0
1
0
0
In
data(even)
In
data(odd)
Byte read of data on DATA[7:0] at an odd address
0
1
1
0
In
x
In
data(odd)
Byte read of data on DATA[15:8] at an even address
0
1
0
1
In
data(even)
In
x
Indicates No Access
1
1
1
1
In
x
In
x
Unimplemented
1
1
1
0
In
x
In
x
11
0
1
In
x
In
x
Table 21-18. Access in Emulation Modes and Special Test Mode
Access
R/W LSTRB ADDR0
DATA[15:8]
DATA[7:0]
I/O
data(addr)
I/O
data(addr)
Word write of data on DATA[15:0] at an even and even+1
address
0
0
0
Out
data(even)
Out
data(odd)
Byte write of data on DATA[7:0] at an odd address
0
0
1
In
x
Out
data(odd)
Byte write of data on DATA[15:8] at an even address
0
1
0
Out
data(odd)
In
x
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
0
1
1
Out data(odd+1) Out
data(odd)
Word read of data on DATA[15:0] at an even and even+1
address
1
0
0
In
data(even)
In
data(even+1)
Byte read of data on DATA[7:0] at an odd address
1
0
1
In
x
In
data(odd)
Byte read of data on DATA[15:8] at an even address
1
1
0
In
data(even)
In
x
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
1
1
1
In
data(odd+1)
In
data(odd)



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