P912XDP512F0MFVR datasheet(140/1350 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

140

Freescale Semiconductor

4.3.2.6

ATD Control Register 5 (ATDCTL5)

This register selects the type of conversion sequence and the analog input channels sampled. Writes to this

enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence

which will then occur on each trigger event. Start of conversion means the beginning of the sampling

phase.

Read: Anytime

Write: Anytime

76543210

DJM

DSGN

SCAN

MULT

Reset

00000000

Figure 4-8. ATD Control Register 5 (ATDCTL5)

Table 4-14. ATDCTL5 Field Descriptions

Field

Description

DJM

Result Register Data Justiﬁcation — This bit controls justiﬁcation of conversion data in the result registers.

See Section 4.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details.

0 Left justiﬁed data in the result registers.

1 Right justiﬁed data in the result registers.

DSGN

Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned

conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed

data is not available in right justiﬁcation. See <st-bold>4.3.2.16 ATD Conversion Result Registers (ATDDRx)

for details.

0 Unsigned data representation in the result registers.

1 Signed data representation in the result registers.

Table 4-15 summarizes the result data formats available and how they are set up using the control bits.

Table 4-16 illustrates the difference between the signed and unsigned, left justiﬁed output codes for an input

signal range between 0 and 5.12 Volts.

SCAN

Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed

continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means

each trigger event starts a single conversion sequence.

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

MULT

Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the

speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel

selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller

samples across channels. The number of channels sampled is determined by the sequence length value (S8C,

S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CC, CB, CA

control bits); subsequent channels sampled in the sequence are determined by incrementing the channel

selection code or wrapping around to AN0 (channel 0.

0 Sample only one channel

1 Sample across several channels

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