P912XDP512F0MFVR datasheet(144/1350 Pages) FREESCALE

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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description

MC9S12XDP512 Data Sheet, Rev. 2.17

144

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FIFOR

FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated

conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because

the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also

practical for non-FIFO modes, and indicates that a result register has been over written before it has been read

(i.e., the old data has been lost). This ﬂag is cleared when one of the following occurs:

• Write “1” to FIFOR

• Start a new conversion sequence (write to ATDCTL5 or external trigger)

0 No over run has occurred

1 Overrun condition exists (result register has been written while associated CCFx ﬂag remained set)

3:0

CC[3:0}

Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion

counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0,

CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6.

If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the

conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion

counters wraps around when its maximum value is reached.

Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the

conversion counter even if FIFO=1.

Table 4-18. ATDSTAT0 Field Descriptions (continued)

Field

Description

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