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PCM1609APT 数据表(PDF) 13 Page - Texas Instruments

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部件名 PCM1609APT
功能描述  24-BIT, 192-kHz SAMPLING, 8-CHANNEL, ENHANCED MULTILEVEL, DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
PDF  43 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

PCM1609APT 数据表(HTML) 13 Page - Texas Instruments

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POWER-ON AND EXTERNAL RESET FUNCTIONS
Reset
Reset Removal
VDD
2.4 V
2 V
1.6 V
Internal Reset
System Clock
T0014-08
0 V
Don’t Care
1024 System Clocks
Reset Removal
1024 System Clocks
RST
Internal Reset
System Clock
Reset
T0015-06
PCM1609A
SLES145A – AUGUST 2005 – REVISED AUGUST 2006
The PCM1609A includes a power-on-reset function, as shown in Figure 20. With the system clock active, and
VDD > 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires
1024 system clocks from the time VDD > 2 V. After the initialization period, the PCM1609A is set to its reset
default state, as described in the Mode Control Registers section of this data sheet.
The PCM1609A also includes an external reset capability using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1609A to initialize to its reset default state. For normal
operation, RST should be set to a logic-1.
The external reset operation and timing is shown in Figure 21. The RST pin is set to logic-0 for a minimum of
20 ns. After the initialization sequence is completed, the PCM1609A is set to its reset default state, as described
in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or VCC/2).
After the reset period, the internal registers are initialized in the next 1/fS period and, if SCKI, BCK, and LRCK
are provided continuously, the PCM1609A provides proper analog output with the group delay time given in the
Electrical Characteristics section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1609A power-up and
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has
been activated.
Figure 20. Power-On-Reset Timing
Figure 21. External Reset Timing
13
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