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CONTROL INTERFACE TIMING REQUIREMENTS

1.4 V

ML

LSB

1.4 V

MC

MDI

LSB

MDI

T0013-05

LSB

MDO

1.4 V

PCM1609A

SLES145A – AUGUST 2005 – REVISED AUGUST 2006

Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register

11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read

operation starts on the next HIGH-to-LOW transition of the ML pin.

The read cycle starts by setting the R/W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All

subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO

is set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the

data contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11,

and where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after

the MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC

clock continues beyond the last physical register (register 19), the read operation returns to control register 1

and subsequent control registers, continuing until ML is set to 1.

Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and

clocks. These timing parameters are critical for proper control-port operation.

SYMBOL

PARAMETER

MIN

MAX

UNITS

MC pulse cycle time

100

ns

MC low-level time

50

ns

MC high-level time

50

ns

ML high-level time

300

ns

ML falling edge to MC rising edge

20

ns

ML hold time (1)

20

ns

MDI hold time

15

ns

MDL setup time

20

ns

MC falling edge to MDO stable

30

ns

(1)

MC rising edge for LSB to ML rising edge.

Figure 27. Control Interface Timing

19

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