STMPE2401 datasheet(24/55 Pages) STMICROELECTRONICS

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Interrupt system

STMPE2401

24/55

9.4

Interrupt status register (ISR)

ISR register monitors the status of the interruption from a particular interrupt source to the

host. Regardless whether the IER bits are enabled or not, the ISR bits are still updated.

Table 22. IER

Bits

Name

Description

8:0

IE[x]

Interrupt Enable Mask (where x = 8 to 0)

IE0 = Wake-up Interrupt Mask

IE1 = Keypad Controller Interrupt Mask

IE2 = Keypad Controller FIFO Overflow Interrupt Mask

IE3 = Rotator Controller Interrupt Mask

IE4 = Rotator Controller Buffer Overflow Interrupt Mask

IE5 = PWM Channel 0 Interrupt Mask

IE6 = PWM Channel 1 Interrupt Mask

IE7 = PWM Channel 2 Interrupt Mask

IE8 = GPIO Controller Interrupt Mask

Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.

ISR_msb

ISR_lsb

Bit

543

Reserved

IS8

IS7

IS6

IS5

IS4

IS3

IS2

IS1

IS0

R/W

Reset

Value

000

Table 23. ISR

Bits

Name

Description

8:0

IS[x]

Interrupt Status (where x = 8 to 0)

Read:

IS0 = Wake-up Interrupt Status

IS1 = Keypad Controller Interrupt Status

IS2 = Keypad Controller FIFO Overflow Interrupt Status

IS3 = Rotator Controller Interrupt Status

IS4 = Rotator Controller Buffer Overflow Interrupt Status

IS5 = PWM Channel 0 Interrupt Status

IS6 = PWM Channel 1 Interrupt Status

IS7= PWM Channel 2 Interrupt Status

IS8 = GPIO Controller Interrupt Status

Write:

A write to a IS[x] bit with a value of ‘1’ will clear the interrupt and a write with a

value of ‘0’ has no effect on the IS[x] bit.

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