All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

Active-HDL automatic simulation mac-

ros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

●

Delivery the documentation updates

●

Phone & email support

SYMBOL

rst

rdcs

wrcs

mdi

dmt(31:0)

waddrmt(8:0)

raddrmt(8:0)

enrmt

enwmt

rxdata(3:0)

rxdv

rxer

rxclk

txdata(3:0)

txen

txer

irq

rd

wr

rdaddr(4:0)

wraddr(4:0)

clk

qmr(31:0)

dmr(31:0)

waddrmr(8:0)

raddrmr(8:0)

enrmr

enwmr

crs

col

txclk

docdbusctrl

mdc

mdo

mdoe

qmt(31:0)

1 – data bus can be configured as 8-, 16- or 32- bit depends

on processor’s bus size

2 – byte enable (be) size is set accordingly to data bus size

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

rdcs

input

Read chip select

wrcs

input

Write chip select

rd

input

Read data strobe

wr

input

Write data strobe

rdaddr(4:0)

input

Host read address bus

wraddr(4:0)

input

Host write address bus

be(3:0)

2

input

Host byte enable

datai(31:0)

1

input

Host output data bus

qmr(31:0)

input

RX DPRAM data output

qmt(31:0)

input

TX DPRAM data output

rxdata(3:0)

input

Ethernet receive data

rxdv

input

Ethernet receive data valid

rxer

input

Ethernet receive error

rxclk

input

Ethernet receive clock

txclk

input

Ethernet transmit clock

crs

input

Ethernet carrier sense

col

input

Ethernet collision detection

mdi

input

Management data input

docdbusctrl

input

DoCD debugger input

datao(31:0)

1

output Host input data bus

irq

output Interrupt signal

dmr(31:0)

output RX DPRAM data input

waddrmr(8:0)

output RX DPRAM write address

raddrmr(8:0)

output RX DPRAM read address

enrmr

output RX DPRAM read enable

enwmr

output RX DPRAM write enable

dmt(31:0)

output TX DPRAM data input

waddrmt(8:0)

output TX DPRAM write address

raddrmt(8:0)

output TX DPRAM read address

enrmt

output TX DPRAM read enable

enwmt

output TX DPRAM write enable

txer

output Ethernet transmit error

txen

output Ethernet transmit enable

txdata(3:0)

output Ethernet transmit data

mdc

output Management clock

mdo

output Management data output

mdoe

output Management data output enable

clk

input

Global clock

rst

input

Global reset

rdcs

input

Read chip select

wrcs

input

Write chip select