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Communications systems

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Media Access Controller

ver 2.07

OVERVIEW

The DMAC is hardware implementation of

media access control protocol defined by the

IEEE standard. DMAC in cooperation with

external PHY device enables network func-

tionality in design. It is capable of transmitting

and receiving Ethernet frames to and from

the network. Half and full duplex modes are

supported, as well 10 and 100 Mbit/s speed.

The core is able to work with wide range of

processors: 8, 16 and 32 bit data bus, with

little or big endian byte order format. Design

is technology independent and thus can be

implemented in variety of process technolo-

gies. This core strictly conforms to IEEE

802.3 standard.

KEY FEATURES

Conforms to IEEE 802.3-2002 specifica-

tion

8/16/32-bit CPU slave interface with little

or big endianess

Simple interface allows easy connection

to CPU

Narrow address bus with indirect I/O in-

terface to the transmit and receive data

dual port memories

Supports

10BASE-T

and

100BASE-

TX/FX IEEE 802.3 compliant MII PHYs

Media Independent Interface (MII) for

connection to external 10/100 Mbps PHY

transceivers

Supports full and half duplex operation at

10 Mbps or 100 Mbps

CRC-32 algorithm calculates the FCS

nibble at a time, automatic FCS genera-

tion and checking, able to capture frames

with CRC errors if required

Lite design, small gate count and fast

operation

Programmable or fixed MAC address

Promiscuous mode support

Dynamic PHY configuration by MII man-

agement interface

Receive FIFO able to store many mes-

sages at a time

Allows operation from a wide range of

input bus clock frequencies

Fully synthesizable

Static synchronous design with positive

edge clocking and synchronous reset

No internal tri-states

Scan test ready

APPLI C ATIONS

Embedded microprocessor boards

Networking devices (Network Interface

Cards, routers, switches)