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DMAC 数据表(PDF) 3 Page - Digital Core Design |
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DMAC 数据表(HTML) 3 Page - Digital Core Design |
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3 / 4 page ![]() All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl BLOCK DIAGRAM Figure below shows the DMAC IP Core block diagram. Receive module Synchronization logic txclk crs col Transmit module txdata(3:0) txen txer rxclk rxdv clk rst rdcs rd wr wraddr(4:0) datai(31:0) Control & I/O logic irq TX RAM interface TX RAM pins RX FIFO RX RAM pins STA mdi mdc mdo mdoe docdbusctrl be(3:0) rxer rxdata(3:0) datao(31:0) wrcs rdaddr(4:0) Transmit module – Performs transmit man- agement functions, sends frames to Ethernet medium. Receive module – is responsible for receiv- ing frames from the Ethernet. Provides nec- essary functions for frame decapsulation, CRC checking, address recognizing and error detection. Synchronization logic – There are 3 clock domains in the DMAC core. This module per- forms synchronization between these. TX RAM / RX FIFO RAM interfaces – Inter- faces to external dual port memories used by the DMAC core to store received and trans- mitted frames. Control and I/O logic – This module pro- vides interface to CPU/BUS. It exchanges data and control logic with transmit and re- ceive modules, thus controls these to perform transmit and receive operations. STA – Station Management entity provides capability to communicate with PHY by sim- ple serial management interface. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route (all key features have been included): Fmax [MHz] Device Speed grade Logic Cells clk / rxclk / txclk STRATIX II -3 967 + 4 kB RAM 211 / 200 / 175 CYCLONE II -6 1222 + 4 kB RAM 150 / 156 / 152 STRATIX GX -5 1255 + 4 kB RAM 152 / 156 / 138 STRATIX -5 1255 + 4 kB RAM 162 / 147 / 137 CYCLONE -6 1254 + 4 kB RAM 148 / 133 / 133 APEX II -7 1622 + 4 kB RAM 145 / 106 / 111 APEX20KC -7 1622 + 4 kB RAM 127 / 118 / 117 APEX20KE -1 1622 + 4 kB RAM 108 / 99 / 111 APEX20K -1 1622 + 4 kB RAM 86 / 87 / 88 Core performance in ALTERA® devices |
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