Application circuit

ST755C

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Application circuit

To achieve the best performances from switching power supply topology, particular care to

layout drawing is needed, in order to minimize EMI and obtain low noise, jitter free operation

moreover, it ensures the full device functionality. Layout design proposed on demoboard

(see Figure 4.) helps to lower the developing time. Wire lengths must be minimized, filter

the integrated circuit. The 10µH inductor must be chosen built on a core, taking care that

saturation current should be higher than the peak LX switch current. See the Peak inductor

current vs. load current graph (Figure 6.).

(**) C6: Very low noise but poor transient and load response speed.

(***) C3 (alternative to C6): faster transient and load response.

Figure 3.

Typical application circuit