数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADRF5031BCCZN-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADRF5031BCCZN-R7
功能描述  9 kHz to 20 GHz, Nonreflective, Silicon SPDT Switch
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF5031BCCZN-R7 数据表(HTML) 7 Page - Analog Devices

Back Button ADRF5031BCCZN-R7 Datasheet HTML 3Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 4Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 5Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 6Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 7Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 8Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 9Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 10Page - Analog Devices ADRF5031BCCZN-R7 Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 12 page
background image
Data Sheet
ADRF5031
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
analog.com
Rev. A | 7 of 12
Figure 3. Pin Configuration (Top View)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 4, 5, 6, 7, 9, 10, 13, 16, 17, 19, 20
GND
Ground. The GND pins must be connected to the RF and /DC ground of the PCB.
3
RFC
RF Common Port. The RFC pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary
when the RF line potential is equal to 0 V DC. See Figure 4 for the interface schematic.
8
RF1
RF Port 1. The RF1 pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary when the
RF line potential is equal to 0 V DC. See Figure 4 for the interface schematic.
11
VDD
Positive Supply Voltage. See Figure 6 for the interface schematic.
12
CTRL
Control Input Voltage. See Figure 5 for the interface schematic.
14
EN
Enable Input Voltage. See Table 7 for the truth table. See Figure 5 for the interface schematic.
15
VSS
Negative Supply Voltage. See Figure 7 for the interface schematic.
18
RF2
RF Port 2. The RF2 pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary when the
RF line potential is equal to 0 V DC. See Figure 4 for the interface schematic
EPAD
Exposed Pad. The exposed pad must be connected to the RF and DC ground of the PCB.
INTERFACE SCHEMATICS
Figure 4. RFC, RF1, and RF2 Interface Schematic
Figure 5. EN and CTRL Interface Schematic
Figure 6. VDD Interface Schematic
Figure 7. VSS Interface Schematic



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com