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ams Datasheet

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[v1-07] 2015-Feb-27

AS5510 − Detailed Description

I²C Interface Data

Operating conditions: Tamb = -30 to 85°C, VDD=2.5 to 3.6V (3V

operation) unless otherwise noted.

Figure 13:

I²C Timings

Note(s) and/or Footnote(s):

1. After this time the first clock is generated.

2. A device must internally provide a hold time of at least 120ns (Fast-mode Plus) for the SDA signal (referred to the VIHmin of the SCL)

to bridge the undefined region of the falling edge of SCL.

3. A fast-mode device can be used in standard-mode system, but the requirement tSU.DAT = 250ns must then be met. This is automatically

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL

signal, it must output the next data bit to the SDA line tRmax + TSU.DAT = 1000 + 250 = 1250ns before the SCL line is released.

4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be

considered for bus timing.

Symbol

Parameter

Min

Typ

Max

Units

fSCLK

SCL clock frequency

1

MHz

tBUF

Bus free time; time between STOP and START condition

0.5

μs

tHD.STA

Hold time; (repeated) START condition (1)

0.26

μs

tLOW

LOW period of SCL clock

0.5

μs

tHIGH

HIGH period of SCL clock

0.26

μs

tSU.STA

Setup time for a repeated START condition

0.26

μs

tHD.DAT

Data hold time (2)

0.45

μs

tSU.DAT

Data setup time(3)

50

ns

tR

Rise time of SDA and SCL signals

120

ns

tF

Fall time of SDA and SCL signals (4)

120

ns

tSU.STO

Setup time for STOP condition

0.26

μs