AS5510 datasheet(14/31 Pages) AMSOSRAM

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[v1-07] 2015-Feb-27

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AS5510 − Detailed Description

Figure 14:

I²C Timing Diagram

I²C Modes

The AS5510 supports the I²C bus protocol. A device that sends

data onto the bus is defined as a transmitter and a device

receiving data as a receiver. The device that controls the

message is called a master. The devices that are controlled by

the master are referred to as slaves. A master device that

generates the serial clock (SCL), controls the bus access and

generates the START and STOP conditions must control the bus.

The AS5510 operates as a slave on the I²C bus. Within the bus

specifications a standard mode (100 kHz maximum clock rate)

a fast mode (400 kHz maximum clock rate) and fast mode plus

(1MHz maximum clock rate) are defined. The AS5510 works in

all three modes. Connections to the bus are made through the

open-drain I/O lines SDA and the input SCL. Clock stretching is

not included.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as start or stop

signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy

Both data and clock lines remain HIGH.

Start Data Transfer

A change in the state of the data line, from HIGH to LOW, while

the clock is HIGH, defines a START condition.

Stop Data Transfer

A change in the state of the data line, from LOW to HIGH, while

the clock line is HIGH, defines the STOP condition.

SDA

SCL

Start

Stop

tbuf

tLOW

tHD.STA

tHIGH

tSU.DAT

tSU.STA

tHD.STA

tSU.STO

Repeated

Start

tHD.DAT

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