ADBMS1818ASWAZ-R7 datasheet(55/92 Pages) AD

55 / 92 page

Data Sheet

ADBMS1818

THEORY OF OPERATION

analog.com

Rev. B | 55 of 92

Figure 85. Reversible isoSPI State Diagram

When ADBMS1818 is in the sleep state, the device responds to

a valid wake-up signal on either Port A or Port B. This is true for

either configuration of the ISOMD pin.

If the wake-up signal is sent on Port A, ADBMS1818 transmits a

long +1 isoSPI pulse (CSB rising) on Port B after the isoSPI is

powered up. If the wake-up signal is sent on Port B, ADBMS1818

powers up the isoSPI but does not transmit a long +1 isoSPI pulse

on Port A.

When ADBMS1818 is in the ready state, communication can be

initiated by sending a long –1 isoSPI pulse (CSB falling) on either

Port A or Port B. The ADBMS1818 automatically configures the port

that receives the long –1 isoSPI pulse as the slave and the other

port is configured as the master. The isoSPI pulses are transmitted

through the master port to the rest of the devices in the daisy chain.

In the active state, the ADBMS1818 is in the middle of the com-

munication and CSB of the internal SPI port is low. At the end

of communication a long +1 pulse (CSB rising) on the slave port

returns the device to the ready state. Although it is not part of

a normal communication routine, the ADBMS1818 allows Port A

and Port B to be swapped inside the active state. This feature

is useful for the master controller to reclaim control of the slave

port of ADBMS1818, irrespective of the current state of the ports.

This action can be done by sending a long –1 isoSPI pulse on the

master port after a time delay of tBLOCK from the last isoSPI signal

that was transmitted by the device. Any long isoSPI pulse sent to

the master port inside tBLOCK is rejected by the device. This ensures

the ADBMS1818 cannot switch ports because of signal reflections

from poorly terminated cables (<100 m cable length).

Timing Diagrams

Figure 86 shows the isoSPI timing diagram for a read command to

daisy-chained ADBMS1818 devices. The ISOMD pin is tied to V–

on the bottom part so that its Port A is configured as an SPI port

(CSB, SCK, SDI, and SDO). The isoSPI signals of three stacked

devices are shown labeled with the port (Port A or Port B) and part

number. Note that ISO B1 and ISO A2 are actually the same signal,

but shown on each end of the transmission cable that connects Part

1 and Part 2. Likewise, ISO B2 and ISO A3 are the same signal, but

with the cable delay shown between Part 2 and Part 3.

Bit WN to Bit W0 refer to the 16-bit command code and the 16-bit

PEC of a read command. At the end of Bit W0, the three parts

decode the read command and begin shifting out data, which is

valid on the next rising edge of clock SCK. Bit XN to Bit X0 refer

to the data shifted out by Part 1. Bit YN to Bit Y0 refer to the data

shifted out by Part 2, and Bit ZN to Bit Z0 refer to the data shifted

out by Part 3. All this data is read back from the SDO port on Part 1

in a daisy-chained fashion.

ADBMS1818ASWAZ-R7 数据表(PDF) 55 Page - Analog Devices

ADBMS1818ASWAZ-R7 数据表(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

数据表下载