F1953 Datasheet

© 2022 Renesas Electronics Corporation

3

February 9, 2022

F1953 SPECIFICATION (31.5 dB Range)

Specifications apply at VDD = +3.0 V, fRF = 2000 MHz, TC= +25°C, VMODE > VIH (Serial Mode) EVkit losses are de-embedded.

Parameter

Comment

Sym

Min

Typ

Max

Units

Logic Input High

CLK, DATA, LE,

VMODE,

D[5:0]

VIH

0.7xVDD

VDD

V

Logic Input Low

CLK, DATA, LE,

VMODE,

D[5:0]

VIL

0.3xVDD

V

Logic Current

VMODE, D[5:0]

IIH, IIL

-5

+5

μA

Logic Current

LE

IIH, IIL

-35

+35

μA

Supply Current

Total VDD = 3V

IDD

0.16

0.25

1

mA

RF1,RF2 Return Loss

20*log(S11), 20*log(S22)

S11,S22

-23

dB

Minimum Attenuation

D[5:0] = [000000]

AMIN

1.35

1.90

dB

Maximum Attenuation

D[5:0] = [111111]

AMAX

32.0

32.4

dB

Minimum Gain Step

Least Significant Bit

LSB

0.50

dB

Phase Delta

Phase change AMIN vs. AMAX

ΦΔ

39

deg

Differential ATTN Error

Between adjacent steps

DNL

0.09

dB

Integral ATTN Error

Error vs. line (AMIN ref) to

13.5dB ATTN

INL1

0.20

0.60

dB

Integral ATTN Error

Error vs. line (AMIN ref) to

31.5dB ATTN

INL2

0.47

0.75

dB

Input IP3

D[5:0] = [000000] = AMIN

D[5:0] = [011111] = A15.5

D[5:0] = [111111] = AMAX

 P

IN = +10 dBm per tone

 50 MHz Tone Separation

IP3I1

IP3I2

IP3I3

+572

+53

+53

+66

+60

+60

dBm

0.1 dB Compression

Please note ABS MAX PIN on Page 2

 D[5:0] = [000101] = A

2.5

 Baseline P

IN = 20dBm

P0.1

28.5

dBm

Settling Time (parallel mode)

 Start LE rising edge > V

IH

 End +/-0.10dB Pout settling

 15.5 – 16.0 transition

TLSB

400

ns

Serial Clock Speed

SPI 3 wire bus

FCLK

10

50

MHz

Serial Setup Time

From rising edge of Vmode to

rising edge of CLK for D5

A

20

ns

Clock width

Clock high pulse width

B

10

ns

LE setup time

From rising edge of CLK pulse

for D0 to LE rising edge

C

10

ns

LE pulse

LE minimum pulse width

D

30

ns

SPECIFICATION NOTES:

1 – Items in min/max columns in bold italics are confirmed by Test.

2 – All other Items in min/max columns are confirmed by Design Characterization.