F1953 Datasheet

© 2022 Renesas Electronics Corporation

4

February 9, 2022

SERIAL CONTROL

Serial mode is selected when VMODE is pulled high (> VIH), In serial mode the F1953 attenuation setting is

programmed via the 3 wire bus (LE, CLK, DATA). In serial mode data is clocked in MSB first. Note the

timing diagram below.

Note – The F1953 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when

the device is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and

DATA will not be clocked into the shift register. It is recommended that LE be pulled high (> VIH) when the

device is not being programmed.

SERIAL REGISTER DEFAULT CONDITION

If the device is powered up in Serial Mode, the device will default to whatever attenuation state is defined by

the six parallel data input pins D5,D4,D3,D2,D1,D0 thus allowing any attenuation setting to be specified as

the power up state.

SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)

SERIAL REGISTER TIMING TABLE

Interval

Symbol

Description

Min

Spec

Max

Spec

Units

A

From rising edge of Vmode to rising edge of CLK for D5

20

ns

B

Clock high pulse width

10

ns

C

From rising edge of CLK pulse for D0 to LE rising edge

10

ns

D

LE minimum pulse width

30

ns

E

Serial data set-up time before clock rising edge

10

ns

F

Serial data hold time after clock rising edge

10

ns