Parallax SX20AC/SX28AC

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Page 39 of 51

Rev 1.6 11/20/2006

16.1.

Equivalent Assembler Mnemonics

Some

assemblers

support

additional

instruction

mnemonics that are special cases of existing instructions

or alternative mnemonics for standard ones. For example,

an assembler might support the mnemonic “CLC” (clear

carry), which is interpreted the same as the instruction

“clrb $03.0” (clear bit 0 in the STATUS register). Some

of the commonly supported equivalent assembler

mnemonics are described in Table 16-7.

Table 16-7: SX Equivalent Assembler Mnemonics

Syntax

Description

Equivalent

Cycles

CLC

Clear Carry bit

CLRB $03.0

1

CLZ

Clear Zero bit

CLRB $03.2

1

JMP W

Jump Indirect W

MOV $02,W

4 or 3 (see Note 1)

JMP PC+W

Jump Indirect W Relative

ADD $02,W

4 or 3 (see Note 1)

MODE imm4

Move Immediate to MODE

Register

MOV M,#lit

1

NOT W

Complement of W

XOR W,#$FF

1

SC

Skip if Carry bit set

SB $03.0

1 or 2 (see Note 2)

SKIP

Skip Next Instruction

SNB $02.0 or SB $02.0

4 or 2 (see Note 3)

Note 1: The JMP W and JMP PC+W instructions take 4 cycles in the Slow clocking mode, or 3 cycles in the Turbo clocking mode.

Note 2: The SC instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true.

Note 3: The assembler converts the SKIP instruction into a SNB or SB instruction that tests the least significant bit of the program

counter, choosing SNB or SB so that the tested condition is always true. The instruction takes 4 cycles in the Slow clocking mode

or 2 cycles in theTurbo clocking mode.