SX28ACSLASHDP datasheet(9/51 Pages) PARALLAX

9 / 51 page

Parallax SX20AC/SX28AC

www.parallax.com

Page 9 of 51

Rev 1.6 11/20/2006

3.0

PORT DESCRIPTIONS

All models contain a 4-bit I/O port (Port A), an 8-bit I/O

port (Port B). The SX28 also contains a second 8-bit I/O

port (Port C). Port A provides symmetrical drive

capability. Each port has three associated 8-bit registers

(Direction, Data, TTL/CMOS Select, and Pull-Up Enable)

to configure each port pin as Hi-Z input or output, to

select TTL or CMOS voltage levels, and to enable/disable

the weak pull-up resistor. The upper four bits of the

registers associated with Port A are not used. The least

significant bit of the registers corresponds to the least

significant port pin. To access these registers, an

appropriate value must be written into the MODE

initialized to “1”. The associated registers allow for each

port bit to be individually configured under software

controls as shown below.

Table 3-1: Port Configuration

Data Direction Registers:

RA, RB, RC

TTL/CMOS Selected Registers:

LVL_A, LVL_B, LVL_C

Pullup Enable Registers:

PLP_A, PLP_B, PLP_C

Output

Hi-Z Input

CMOS

TTL

Enable

Disable

Figure 3-1

Port A Configuration

3.1.

Reading and Writing the Ports

The three ports are memory-mapped into the data memory

address space. To the CPU, the three ports are available as

the RA, RB, and RC file registers at data memory

addresses 05h, 06h, and 07h, respectively. Writing to a

port data register sets the voltage levels of the

corresponding port pins that have been configured to

operate as outputs to a corresponding level, 1 = 5 V,

0 = 0 V. Reading from a register reads the voltage levels

of all port pins.

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