CC2400-RTR1 datasheet(62/84 Pages) TI2

62 / 84 page

CC2400

SWRS042A

Page 62 of 83

FREQEST (0x07) - Received frequency offset estimation

Bit

Field Name

Reset

R/W

Description

15:8

RX_FREQ_OFFSET[7:0]

Estimate of the received signals centre frequency comparison to

the ideal 1 MHz centre frequency. Two's complement signed

value. See page 42.

7:0

Reserved, write as 0.

IOCFG (0x08) - I/O configuration register

Bit

Field Name

Reset

R/W

Description

Reserved, write as 0.

14:9

GIO6_CFG[5:0]

R/W

Configuration of the GIO6 pin. See page 45 for options. The

reset value outputs the signal CRC_OK on pin GIO6.

8:3

GIO1_CFG[5:0]

R/W

How to use the GIO1 pin. See page 45 for options. The reset

value outputs the signal LOCK_STATUS on pin GIO1.

2:0

HSSD_SRC[2:0]

R/W

For test purposes only.

The HSSD (High Speed Serial Data) test module is used as

follows:

0: Off.

1: Output AGC status (gain setting / peak detector status /

accumulator value)

2: Output ADC I and Q values.

3: Output I/Q after digital down-mixing and channel filtering.

4: Output RX signal magnitude / frequency unfiltered (from

demodulator).

5: Output RX signal magnitude / frequency filtered (from

demodulator).

6: Output RSSI / RX frequency offset estimation

7: Input DAC values.

The HSSD test module requires that the FS is up and running as

it uses CLK_PRE (~150 MHZ) to produce its ~37.5 MHz data

clock and serialize its output words. Also, in order for HSSD to

function properly GRMDM.PIN_MODE must be set for HSSD.

FSMTC (0x0B) - Finite state machine time constants

Bit

Field Name

Reset

R/W

Description

15:13

TC_RXON2AGCEN[2:0]

R/W

The time in 5 µs steps from RX is turned on until the AGC is

enabled. This time constant must be large enough to allow the

RX chain to settle so that the AGC algorithm starts working on a

proper signal. The default value corresponds to 15 us.

12:10

TC_PAON2SWITCH[2:0]

R/W

The time in µs from TX is started until the TX/RX switch allows

the TX signal to pass.

9:6

RES[9:6]

R/W

Reserved

5:3

TC_TXEND2SWITCH[2:0]

R/W

The time in µs from TX is stopped (for instance the last bit of the

packet is sent) until the RX/TX switch breaks the TX output and

the PKT signal is set.

CC2400-RTR1 数据表(PDF) 62 Page - Texas Instruments

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CC2400-RTR1 数据表(PDF) 62 Page - Texas Instruments

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