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CC2400-RTR1 数据表(PDF) 67 Page - Texas Instruments |
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CC2400-RTR1 数据表(HTML) 67 Page - Texas Instruments |
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67 / 84 page ![]() CC2400 SWRS042A Page 67 of 83 MANOR (0x13) - Manual signal OR override register 3 Bit Field Name Reset R/W Description 15 VGA_RESET_N 0 R/W Overrides VGA_RESET_N used to reset the peak detectors in the VGA in the RX chain. 14 LOCK_STATUS 0 R/W Overrides the LOCK_STATUS top-level signal that indicates whether VCO lock is achieved or not. 13 BALUN_CTRL 0 R/W Overrides the BALUN_CTRL signal that controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch. 12 RXTX 0 R/W Overrides the RXTX signal that controls whether the LO buffers (0) or PA buffers (1) should be used. 11 PRE_PD 0 R/W Power down of prescaler. 10 PA_N_PD 0 R/W Power down of PA (negative path). 9 PA_P_PD 0 R/W Power down of PA (positive path). When PA_N_PD=1 and PA_P_PD =1 the up-conversion mixers are in power down. 8 DAC_LPF_PD 0 R/W Power down of TX DACs. 7 BIAS_PD 0 R/W Power down control of global bias generator + XOSC clock buffer. 6 XOSC16M_PD 0 R/W Power down control of 16 MHz XOSC core. 5 CHP_PD 0 R/W Power down control of charge pump. 4 FS_PD 0 R/W Power down control of VCO, I/Q generator, LO buffers. 3 ADC_PD 0 R/W Power down control of the ADCs. 2 VGA_PD 0 R/W Power down control of the VGA. 1 RXBPF_PD 0 R/W Power down control of complex band-pass receive filter. 0 LNAMIX_PD 0 R/W Power down control of LNA, down-conversion mixers and front- end bias. MDMTST0 (0x14) - Modem Test Register 0 Bit Field Name Reset R/W Description 15:14 - 0 W0 Reserved, write as 0. 13 TX_PRNG 0 R/W When set, the transmitted data is taken from a 10-bit PRNG instead of from the DIO pin in un-buffered mode or from the FIFO in buffered mode. 12 TX_1MHZ_OFFSET_N 0 R/W Determines TX IF frequency: 0: 1 MHz (Not used) 1: 0 MHz (During initialization this bit must be set to a logical ’1’.) 11 INVERT_DATA 0 R/W When this bit is set the data are inverted (internally) before transmission, and inverted after reception. 10 AFC_ADJUST_ON_PACKET 0 R/W When this bit is set to '1', modem parameters are adjusted for slow tracking of the received signal as opposed to quick acquisition when a packet is received in RX. • 3 See footnote for MANAND register (address 0x0D) for description of the use of this register. |
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