PCF8563

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 11 — 26 October 2015

6 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.

Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address,

an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which

provides the source clock for the Real-Time Clock (RTC) and calender, a programmable

clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I2C-bus interface.

All 16 registers are designed as addressable 8-bit parallel registers although not all bits

are implemented. The first two registers (memory address 00h and 01h) are used as

control and/or status registers. The memory addresses 02h through 08h are used as

counters for the clock function (seconds up to years counters). Address locations 09h

through 0Ch contain alarm registers which define the conditions for an alarm.

Address 0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the Timer_control

and Timer registers, respectively.

The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm,

Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD)

format.

When one of the RTC registers is written or read, the contents of all time counters are

frozen. Therefore, faulty writing or reading of the clock and calendar during a carry

condition is prevented.

8.1 CLKOUT output

A programmable square wave is available at the CLKOUT pin. Operation is controlled by

the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),

1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller

clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain

output and enabled at power-on. If disabled it becomes high-impedance.

8.2 Register organization

Table 4.

Formatted registers overview

Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they

could be either logic 0 or logic 1. After reset, all registers are set according to Table 27.

Address

Register name

Bit

7

6

5

4

3

2

1

0

Control and status registers

00h

Control_status_1

TEST1

N

STOP

N

TESTC

N

N

N

01h

Control_status_2

N

N

N

TI_TP

AF

TF

AIE

TIE

Time and date registers

02h

VL_seconds

VL

SECONDS (0 to 59)

03h

Minutes

x

MINUTES (0 to 59)

04h

Hours

x

x

HOURS (0 to 23)

05h

Days

x

x

DAYS (1 to 31)

06h

Weekdays

x

xxxxWEEKDAYS (0 to 6)

07h

Century_months

C

x

x

MONTHS (1 to 12)

08h

Years

YEARS (0 to 99)