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PCM3052ARTF.B 数据表(PDF) 23 Page - Texas Instruments |
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PCM3052ARTF.B 数据表(HTML) 23 Page - Texas Instruments |
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23 / 48 page ![]() www.ti.com VCC1, VDD 0 V LRCK, BCK, SCKI DOUT 1024 SCKI Internal Reset Synchronous Clocks Power Down Normal Operation ZERO PDWN VOUTL, VOUTR (VCC1 = 5 V, VDD = 3.3 V Typ) (VCC1 = 3.9 V, VDD = 2.2 V Typ) DOUTS t(DACDLY1), 2100 /fS VCOM (0.5 VCC2) About 40/fS t(ADCDLY1), 4500 /fS Enable if S/PDIF Bit = HIGH Disable T0097-01 PCM3052A SLES160 – NOVEMBER 2005 DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/fS following PDWN release. Notes: 1. Large pop noises can be generated on VOUTL and VOUTR if the power supply is turned off during normal operation. 2. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out. 3. Changing mode controls during normal operation can degrade analog performance. It is recommended that mode controls be changed through the serial control port, and that changing or stopping the clock, switching the power supply off, etc., be done in the power-down mode. Figure 44. DAC Output and ADC Output for Power-On Reset 23 |
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