PCM3052ARTF.B datasheet(32/48 Pages) TI2

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Write Operation

R0002-03

M: Master Device S: Slave Device

St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition

Transmitter

Data Type

Slave Address

ACK

Reg Address

Write Data 1

ACK

Write Data 2

ACK

Serial Control Enable/Disable

T0100-01

µs (min)

Don’t Care

Enable

Disable

I2CEN

SDA/SCL

HIGH Fixed

Don’t Care

ADR

HIGH or LOW

PCM3052A

SLES160 – NOVEMBER 2005

The PCM3052A supports receiver function. A master can write to any PCM3052A registers using single or

multiple accesses. The master sends a PCM3052A slave address with a write bit, a register address, and the

data. If multiple access is required, the address is that of the starting register, followed by the data to be

transferred. When the data are received properly, the index register is incremented by 1 automatically. When the

index register reaches 50h, the next value is 41h. When undefined registers are accessed, the PCM3052A does

not send an acknowledgement. Figure 53 is a diagram of the write operation. The register address and the write

data are 8 bits and MSB-first format.

Figure 53. Framework for Write Operation

The PCM3052A supports I2C serial control enable/disable function by I2CEN (pin 21) to avoid an unstable start

condition. When the I2CEN pin transitions from LOW to HIGH, both SDA (pin 18) and SCL (pin 19) must be

HIGH stable and the ADR (pin 20) must be also stable.

While I2CEN = LOW, the write operation is disabled. A timing chart of I2CEN is shown in Figure 54.

Figure 54. I2CEN Timing Chart

PCM3052ARTF.B 数据表(PDF) 32 Page - Texas Instruments

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