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REGISTER DEFINITIONS

ATx[7:0]: Digital Attenuation Level Setting (DAC)

MRST: Mode Control Register Reset (ADC and DAC)

SRST: System Reset (ADC and DAC)

PCM3052A

SLES160 – NOVEMBER 2005

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 65

0

1

0

0

0

0

0

1

AT17

AT16

AT15

AT14

AT13

AT12

AT11

AT10

REGISTER 66

0

1

0

0

0

0

1

0

AT27

AT26

AT25

AT24

AT23

AT22

AT21

AT20

Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).

Default value: 1111 1111b

ATX[7:0]

DECIMAL VALUE

ATTENUATION LEVEL SETTING

1111 1111b

255

0 dB, No Attenuation. (default)

1111 1110b

254

–0.5 dB

1111 1101b

253

–1.0 dB

:

:

:

1000 0011b

131

–62.0 dB

1000 0010b

130

–62.5 dB

1000 0001b

129

–63.0 dB

1000 0000b

128

Mute

:

:

:

0000 0000b

0

Mute

Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set

from 0 dB to –63 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level

change from current value to target value is performed by incrementing or decrementing by one small step size

for every 1/fS time interval during 2048/fS. The small step size is determined automatically so that it can provide a

transition in attenuation level with a characteristic S-shaped curve from the current value to the target value.

While the attenuation level change sequence is in progress for 2048/fS, processing of the attenuation level

change for any new command is ignored, and the new command is overwritten into command buffer. The last

command for an attenuation level change is performed after present attenuation level change sequence is

finished.

The attenuation data for each channel can be set individually. The attenuation level can be calculated using the

following formula:

Attenuation level (dB) = 0.5

× (ATx[7:0]

DEC – 255)

where ATx[7:0]DEC = 0 through 255.

For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation.

The preceding table shows attenuation levels for various settings.

B15

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

REGISTER 67

0

1

0

0

0

0

1

1

MRST

SRST

ADPSV

DAPSV

RSV

RSV

RSV

RSV

Default value: 1

MRST = 0

Set default value

MRST = 1

Normal operation (default)

The MRST bit controls mode control register reset. Pop-noise may be generated.

Default value: 1

35