Data Sheet

ADRF5051

APPLICATIONS INFORMATION

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Rev. A | 16 of 18

The ADRF5051 has two power supply pins (VDD and VSS) and

four control pins (LS, EN, V1, and V2). Figure 27 shows the exter-

nal components and connections for the supply and control pins.

The supply and control pins are decoupled with 100pF multilayer

ceramic capacitors. Place the decoupling capacitors as close as

possible to the ADRF5051. The device pinout allows the placement

of the decoupling capacitors close to the ADRF5051. No other

external components are required for bias and operation, except

DC blocking capacitors on the RF pins when the RF lines are

biased at a voltage different than 0V. Refer to Pin Configuration and

Function Descriptions section for additional information.

Figure 27. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50Ω internally, and the pinout is

designed to mate a coplanar waveguide (CPWG) with a 50Ω char-

acteristic impedance on the PCB. Figure 28 shows the referenced

CPWG RF trace design for an RF substrate with 8mil thick Rogers

RO4003 dielectric material. RF trace with 14mil width and 7mil

clearance is recommended for 1.5mil finished copper thickness.

Figure 28. Example PCB Stack-Up

Figure 29 shows the routing of the RF traces, supply, and control

signals from the ADRF5051. The ground planes are connected with

as many filled, through vias as are allowed for optimal RF and

thermal performance. The primary thermal path for the device is the

bottom side.

Figure 29. PCB Routings

Figure 30 shows the recommended layout from the device RF pins

to the 50Ω CPWG on the referenced stack-up. PCB pads are drawn

1:1 to the device pads. The ground pads are drawn solder mask

defined, and the signal pads are drawn as pad defined. The RF

trace from the PCB pad is extended to the device edge and tapered

to the RF trace with a 45° angle. The paste mask is designed to

match the pad without any aperture reduction. The paste is divided

into multiple openings for the paddle.

Figure 30. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, contact Analog Devices, Inc., Technical Support

Request for further recommendations.