STM7710

Architecture

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Architecture

2.1

Architecture overview

The STM7710 is designed around the well-proven STBus interconnect.

Transport streams are received and processed by the TS subsystem. The resulting PES

streams and section data are stored in memory buffers in DDR SDRAM attached to the

local memory interface (LMI).

A flexible DMA controller (FDMA) performs PES parsing and start code detection. It routes

elementary streams to audio and video bit buffers in DDR SDRAM. An MP@HL video

decoder decodes HD or SD video streams. Audio decoding and PCM mixing is performed

by the MMDSP and output through S/PDIF or integrated 24-bit stereo DACs.

After video decoding, two independently formatted video displays (main and auxiliary) can

be generated, and each mixed independently with graphics to create main and auxiliary

display compositions. The main display composition (HD or SD) can be output as RGB or

YPbPr analog component video and digitally through a copy-protected DVI/HDMI interface.

The auxiliary display composition (SD only) can be output as a YPbPr analog component or

as composite video on a separate interface for connection to a VCR.

A digital video input interface allows the STM7710 to receive SD uncompressed digital

video and to output this to the main and auxiliary displays in place of decoded video. A

separate PCM input allows any associated audio to be received, mixed and output in place

of decoded audio.

The graphics subsystem comprises a separate 2D-blitter, two graphics planes, a cursor

plane and dual display compositor. Graphics buffers are created, stored in and displayed

from buffers in DDR SDRAM.

The STM7710 embeds an ST20-C1 CPU core for applications and data processing and

device control. The CPU boots from Flash/SFlash on the external memory interface (EMI)

and can execute in place or transfer the main executable to the DDR SDRAM and execute

from there. CPU data is held in DDR SDRAM where cacheable and noncacheable regions

can be programmed. The 16-bit EMI is also used for connecting to external peripherals.

System performance is enhanced with the multichannel FDMA which can be used for 2D

block move and stream data transfers with minimal CPU intervention.

DVR applications are supported using a hard-disk drive (HDD) connected either to the EMI

or to the USB 2.0 HDD interface.

The STM7710 also integrates a range of peripherals, system services and a clock generator

module with embedded VCXO (programmable frequency synthesizers able to replace the

classical external VCXO) to significantly reduce external component cost.

2.2

Processor core

The STM7710 integrates a 200 MHz ST20-C105 processor core composed of the ST20C1+

CPU, a diagnostic controller unit (for low intrusion, real-time debugging), memory (8 Kbyte

instruction cache, 8 Kbyte data cache and 4 Kbyte SRAM) and a 16 priority-level interrupt

controller.