Architecture

STM7710

12/23

2.6

MPEG-2 video decoder

The STM7710's video decoder is a single-stream decoder for either SD or HD streams. The

decoder is fully compliant with ISO/IEC13818-2 MP@ML and MP@HL formats.

A stream is decoded picture by picture from an elementary stream buffer. Decoding,

reconstruction and prediction buffers are set up by the CPU. CPU control of bit buffer

pointers provides flexibility for trick modes and out-of-sequence decoding.

Semantic or syntax errors are detected by the decoder and failing macroblocks are replaced

up to the next slice or picture.

Pictures can be reconstructed with decimation for VCR recording to reduce memory

bandwidth while keeping full resolution pictures for anchor frames and main display.

2.7

Digital video input

Digital SD video data can be input to the STM7710 through an 8-bit digital video input port.

The 8-bit mode is intended for inputting SD video data conforming to ITU-R BT656 with

embedded syncs or ITU-R BT601 with external syncs. In ITU-R BT656 mode, auxiliary data

embedded in the stream can be extracted to a separate buffer.

2.8

Video display processors

The STM7710 displays video using the main and auxiliary display processors (Figure 5).

The video may have been decoded and reconstructed by the MPEG decoder or acquired

through the digital video interface.

Figure 5.

Display composition and output

Main

video display

processor

Cursor

GDP1

GDP2

VID1

Mixer 1

Mixer 2

Auxiliary

output stage

Main

output stage

Main

display

composition

Auxiliary

display

composition

Cursor

Graphics 1

Graphics 2

BCK

DVI-HDCP

HDMI

Main analog

outputs

YPbPr or RGB

Auxiliary analog

outputs

YPbPr or YC,

STBus

VID2

Auxiliary

video display

processor

CVBS