ISL85415

7. Application Guidelines

FN8373 Rev.5.01

Page 26 of 30

Jun.4.20

Figure 62 shows the type II compensator and its transfer function is expressed, as shown in Equation 10:

where

Compensator design goal:

• High DC gain

• Choose Loop bandwidth fc less than 100kHz

• Gain margin: >10dB

• Phase margin: >40°

The compensator design procedure is as follows:

The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is

determined by Equation 11.

where GM is the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is

then given by Equation 12.

Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either

ESR zero frequency or half switching frequency, whichever is lower in Equation 12. An optional zero can boost

the phase margin. ωCZ2 is a zero due to R2 and C3.

Put compensator zero two to five times fc

Example: VIN = 12V, VO = 5V, IO = 500mA, fSW = 500kHz, R2 = 90.9kΩ, Co = 22µF/5mΩ, L = 39µH, fc = 50kHz,

then compensator resistance R6:

(EQ. 10)

Av S



vˆCOMP

vˆFB

------------------

GM R3



C6 C7

+

 R

2

R3

+





-------------------------------------------------------

1

S



cz1

------------

+



 1

S



cz2

------------

+





S1

S



cp1

------------

+



 1

S



cp2

------------

+





-------------------------------------------------------------

=

=



cz1

1

R6C6

--------------



cz2

1

R2C3

--------------

=



cp1



C6 C7

+

R6C6C7

----------------------



cp2

R2 R3

+

C3R2R3

----------------------

=



=

,

=

(EQ. 11)

R6

2

f

cVoCoRt

GM VFB



--------------------------------

27.3

3

10 f

cVoCo



==

(EQ. 12)

C6

RoCo

R6

--------------

VoCo

IoR6

-------------- C7 max

RcCo

R6

--------------

1

f

sR6

---------------

(,

)

=

,

=

=

(EQ. 13)

C3

1

f

cR2

---------------

=

(EQ. 14)

R6

27.3

3

10 50kHz 5V 22F







150.2k



==