ST7262 datasheet(53/139 Pages) STMICROELECTRONICS

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ST7262

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10.3 TIMEBASE UNIT (TBU)

10.3.1 Introduction

The Timebase unit (TBU) can be used to generate

periodic interrupts.

10.3.2 Main Features

■ 8-bit upcounter

■ Programmable prescaler

■ Period between interrupts: max. 8.1ms (at 8

MHz fCPU )

■ Maskable interrupt

■ Cascadable with PWM/ART TImer

10.3.3 Functional Description

The TBU operates as a free-running upcounter.

When the TCEN bit in the TBUCSR register is set

by software, counting starts at the current value of

the TBUCV register. The TBUCV register is incre-

mented at the clock rate output from the prescaler

selected by programming the PR[2:0] bits in the

TBUCSR register.

When the counter rolls over from FFh to 00h, the

OVF bit is set and an interrupt request is generat-

ed if ITE is set.

The user can write a value at any time in the

TBUCV register.

If the cascading option is selected (CAS bit=1 in

the TBUCSR register), the TBU and the the ART

TImer counters act together as a 16-bit counter. In

this case, the TBUCV register is the high order

byte, the ART counter (ARTCAR register) is the

low order byte. Counting is clocked by the ART

timer clock (Refer to the description of the ART

Timer ARTCSR register).

10.3.4 Programming Example

In this example, timer is required to generate an in-

terrupt after a delay of 1 ms.

Assuming that fCPU is 8 MHz and a prescaler divi-

sion factor of 256 will be programmed using the

PR[2:0] bits in the TBUCSR register, 1 ms = 32

TBU timer ticks.

In this case, the initial value to be loaded in the

TBUCV must be (256-32) = 224 (E0h).

ld A, E0h

ld TBUCV, A

; Initialize counter value

ld A 1Fh

;

ld TBUCSR, A

; Prescaler factor = 256,

; interrupt enable,

; TBU enable

Figure 38. TBU Block Diagram

TBU 8-BIT UPCOUNTER (TBUCV REGISTER)

INTERRUPT REQUEST

TBU PRESCALER

fCPU

TBUCSR REGISTER

PR1 PR0

PR2

TCEN

ITE

OVF

MSB

LSB

ART PWM TIMER 8-BIT COUNTER

MSB

LSB

CAS

TBU

ART TIMER CARRY BIT

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