ST7262 datasheet(41/139 Pages) STMICROELECTRONICS

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ST7262

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10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

10.1.2 Main Features

■ Programmable free-running downcounter (64

increments of 65536 CPU cycles)

■ Programmable reset

■ Reset (if watchdog activated) when the T6 bit

reaches zero

■ Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the CR register (bits

T[6:0]), is decremented every 65,536 machine cy-

cles, and the length of the timeout period can be

programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

30µs.

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. This downcounter is free-

running: it counts down even if the watchdog is di-

abled The value to be stored in the CR register

must be between FFh and C0h (see Table 14):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 14.Watchdog Timing (fCPU = 8 MHz)

Figure 30. Watchdog Block Diagram

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

524.288

Min

C0h

8.192

RESET

WDGA

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

÷65536

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