PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884

2006-03-30

7

Top View

Cascading Displays

The PDSP188X is designed to drive up to 16 other

PDSP188Xs with input loading of 15 pF each.

General requirements for cascading 16 displays

together:

• Determine the correct address for each display.

• Use CE from an address decoder to select the correct

display.

• Use CE from an address decoder to select the correct

display.

• Select one of the Displays to provide the Clock for the

other displays. Connect CLKSEL to V

play.

• Tie CLKSEL to ground on other displays.

• Use RST to synchronize the blinking between the dis-

plays.

Pin Assignments

Pin #

Name

Symbol

Definition

1

Reset

RST

Initializes display; clears Character

RAM (20H), Flash RAM (00H),

control word (00H), and resets

internal counters. UDC Address

Register and UDC RAM

unaffected.

2

Flash

FL

Accesses Flash RAM. Address

inputs A0–A2 select digit address

while data bit D0 sets (D0=1) or

resets (D0=0) Flash bit, A3 and A4

ignored.

3

Address

input

A0

A0–A2 select specific digits.

See Table „Memory Selection“

(page 9).

4

A1

Same as A0

5

A2

Same as A0

6

Address

input

A3

A3 and A4 access parts of memory

together with Flash pin. See Table

1.

7–9

No pins

—

No connections

10

Address

input

A4

Same as A3

11

Clock

Select

CLS

Selects internal or external clock

source. CLS=1 selects internal

clock (master), CLS=0 selects

external clock (slave operation).

12

Clock

In/Out

CLK

Inputs or outputs clock as

determined by CLS.

13

Write

WR

Writes data into display when

WR=0. Note CE=0 to enable write

cycle.

14

Chip

Enable

CE

Enables display’s write and read

cycles when CE=0.

15

Positive

supply

V

CC

Positive power supply input.

IDPA5110

01

2

3

45

67

16

Supply

ground

GND

sup

Analog ground for LED drivers

17

—

NC

No connection

18

Logic

ground

GND

log

Logic ground for digital

circuitry

19

Read

RD

Reads data from display when

RD=0. Also CE=0.

20

Data bit

zero

D0

Least significant data bit.

21

Data bit

one

D1

Second data bit.

22–24

No pins

—

No connections

25

Data bit

two

D2

Third data bit.

26

Data bit

three

D3

Fourth data bit.

27

Data bit

four

D4

Fifth data bit.

28

Data bit

five

D5

Sixth data bit.

29

Data bit

six

D6

Seventh data bit.

30

Data bit

seven

D7

Most significant data bit.

Pin Assignments

Pin #

Name

Symbol

Definition