PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884

2006-03-30

9

Functional Description

The display's user interface is organized into five memory areas.

They are accessed using the Flash Input, FL, and address lines,

A3 and A4. All the listed RAMs and Registers may be read or writ-

ten through the data bus. See Table „Memory Selection“ (page 9).

Each input pin is described in Pin Definitions.

RST can be used to initialize display operation upon power up or

during normal operation. When activated, RST will clear the Flash

RAM and Control Word Register (00H) and reset the internal

counter. All eight display memory locations will be set to 20H to

show blanks in all digits.

FL pin enables access to the Flash RAM. The Flash RAM will set

(D0=1) or reset (D0=0) flashing of the character addressed by A0–

A2.

The 1 x 8 bit Control Word Register is loaded with attribute data if

A3=0.

The Control Word Logic decodes attribute data for proper imple-

mentation.

Character ROM is designed for 128 ASCII characters. The ROM

is Mask Programmable for custom fonts.

The Clock Source could either be the internal oscillator

(CLKSEL=1) of the device or an external clock (CLKSEL=0) could

be an input from another HDSP211X display for synchronizing

blinking for multiple displays.

The Display Multiplexer controls the Row Drivers so no additional

logic is required for a display system.

The Display has eight digits. Each digit has 35 LEDs.

Theory of Operation

The PDSP188X Display is designed to work with all major micro-

processors. Data entry is via an eight bit parallel bus. Three bits of

address route the data to the proper digit location in the RAM.

Standard control signals like WR and CE allow the data to be writ-

ten into the display.

D0–D7 data bits are used for both Character RAM and control

word data input. A3 acts as the mode selector. If A3=1, character

RAM is selected. Then input data bit D7 will determine whether

input data bits D0–D6 is ASCII coded data (D7=0) or UDC data

(D7=1). See section on „UDC Address Register and UDC RAM“

(page 10).

For normal operation FL pin should be held high. When FL is held

low, Flash RAM is accessed to set character blinking.

The seven bit ASCII code is decoded by the Character ROM to

generate Column data. Twenty columns worth of data is sent out

each display cycle, and it takes fourteen display cycles to write into

eight digits.

The rows are multiplexed in two sets of seven rows each. The

internal timing and control logic synchronizes the turning on of

rows and presentation of column data to assure proper display

operation.

Power Up Sequence

Upon power up the display will come on at random. Thus the dis-

play should be reset on power-up. Reset will clear the Flash

RAM, Control Word Register and reset the internal counter. All

the digits will show blanks and display brightness level will be

100%.

The display must not be accessed until three clock pulses (110 µs

minimum using the internal clock) after the rising edge of the reset

line.

Microprocessor Interface

The interface to a microprocessor is through the 8-bit data bus

(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE

and WR.

To write data (ASCII/Control Word) into the display CE should be

held low, address and data signals stable and WR should be

brought low. The data is written on the low to high transition of

WR.

The Control Word is decoded by the Control Word Decode Logic.

Each code has a different function. The code for display brightness

changes the duty cycle for the column drivers. The peak LED cur-

rent stays the same but the average LED current diminishes

depending on the intensity level.

The character Flash Enable causes 2.0 Hz coming out of the

counter to be ANDED with the column drive signal to make the col-

umn driver cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.

Five Basic Memory Areas

Character RAM

Stores either ASCII (Katakana)

character data or an UDC RAM

address

Flash RAM

1 x 8 RAM which stores Flash data

User-Defined

Character RAM

(UDC RAM)

Stores dot pattern for custom

characters

User-Defined Address

Register (UDC Address

Register)

Provides address to UDC RAM

when user is writing or reading

custom character

Control Word

Register

Enables adjustment of display

brightness, flash individual

characters, blink, self test or clearing

the display

Memory Selection

FL

A4

A3

Section of Memory

A2–A0

Data Bits Used

0X

X

Flash RAM

Character Address

D0

10

0

UDC Address Register

Don’t Care

D3–D0

10

1

UDC RAM

Row Address

D4–D0

11

1

Character RAM

Character Address

D7–D0

11

0

Control Word Register

Don’t Care

D7–D0