PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884

2006-03-30

11

Flash RAM

The Flash RAM allows the display to flash one or more of the char-

acters being displayed. The Flash Ram is accessed by setting FL

low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with

each bit corresponding to a digit address. Digit 0 is on the left side

of the display and digit 7 is on the right side of the display. Address

lines, A2–A0 select the digit address with A2 being the most signif-

icant digit and A0 being the least significant digit. Data bit, D0, sets

and resets the flash bit for each digit. When D0 is high, the flash bit

is set; and when D0 is low, it is reset. See Table „Flash RAM

Access Logic“ (page 11).

Control Word

The Control Word is used to set up the attributes required by the

user. It is addressed by setting FL=1, A4=1, A3=0. The Control

Word is an 8 bit register and is accessed using data bits, D7–D0.

See Table „Control Word Access Logic“ (page 11) and Figure

„Control Word Data Definition“ (page 12) for the logic and attrib-

uted control. The Control Word has 5 functions. They are bright-

ness control, flashing character enable, blinking character

enable, self test, and clear (Flash and Character RAMS only).

Brightness Control

Control Word bits, D2–D0, control the brightness of the display

with a binary code of 000 being 100% brightness and 111 being

display blank. See Figure „Control Word Data Definition“

(page 12) for brightness level versus binary code. The average I

CC

can be calculated by multiplying the 100% brightness level I

CC

value by the display’s brightness level. For example, a display set

to 80% brightness with a 100% average I

have an average I

Flash Function

Control Word bit, D3, enables or disables the Flash Function.

When D3 is 1, the Flash Function is enabled and any digit with its

corresponding bit set in the Flash RAM will flash at approximately

2.0 Hz. When using an external clock, the flash rate can be deter-

mined by dividing the clock rate by 28,672. When D3 is 0, the

Flash Function is disabled and the contents of the Flash RAM is

ignored. For synchronized flashing on multiple displays, see the

Reset Section (page 12).

Blink Function

Control Word bit, D4, enables or disables the Blink Function. When

D4 is 1, the Blink Function is enabled and all characters on the dis-

play will blink at approximately 2.0 Hz. The Blink Function will over-

ride the Flash Function if both functions are enabled. When D4 is

0, the Blink Function is disabled. When using an external clock, the

blink rate can be determined by dividing the clock rate by 28,672.

For synchronized blinking on multiple displays, see the Reset Sec-

tion (page 12).

Self Test

Control Word bits, D6 and D5, are used for the Self Test Function.

When D6 is 1, the Self Test is initiated. Results of the Self Test are

stored in bit D5. Control Word bit, D5, is a read only bit. When D5

is 1, Self Test has passed. When D5 is 0, Self Test failed is indi-

cated. The Self Test function of the IC consists of two internal rou-

tines which exercise major portions of the IC and illuminates all of

the LEDs. The first routine cycles the ASCII decoder ROM through

all states and performs a check sum on the out-put. If the check

sum is correct, D5 is set to a 1 (Pass).

UDC Character Map

Row Data

A2

A1

A0

Row #

Column Data

C1

C2

C3

C4

C5

D4

D3

D2

D1

D0

00

0

1

5 x 7

Dot Matrix

Pattern

00

1

2

01

0

3

01

1

4

10

0

5

10

1

6

11

0

7

Flash RAM Access Logic

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

0

1

0

X

X

Flash RAM Address

for Digits 0–7

D0=Flash Data, 0=Flash Off and 1=Flash On

(Write Cycle)

1

0

1

0

0

X

X

Flash RAM Address

for Digits 0–7

D0=Flash Data, 0=Flash Off and 1=Flash On

(Read Cycle)

Control Word Access Logic

RST

CE

WR

RD

FL

A4

A3

A2

A1

A0

D7 D6 D5 D4 D3 D2 D1 D0

1

0

0

1

1

1

0

Not used for Control

Word

Control Word data for a Write Cycle,

see Figure „Control Word Data Definition“

(page 12)

1

0

1

0

1

1

0

Not used for Control

Word

Control Word data for a Read during a

Read Cycle